IUNET - Italy

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The “Consorzio Nazionale Interuniversitario per la Nanoelettronica” (IUNET, Italian Universities Nano-Electronics Team), is a non-profit organization, aimed to lead and coordinate the effort of the major Italian university teams in the field of nanoelectronic device modelling and characterization. Current members of IUNET are the Universities of Bologna, Calabria, Ferrara, Modena e Reggio Emilia, Padova, Perugia, Pisa, Roma, Udine, Politecnico of Milano and Politecnico of Torino. They offer complementary expertise in the fields of modelling, simulation and characterization of CMOS-based, memory and Beyond CMOS nanometer-size devices. IUNET technical reputation is confirmed by many projects where it has been partner in the 5th, 6th and 7th FP and H2020 programmes, and the ENIAC and ECSEL JU calls, including, among others, the NANOFUNCTION project on sensors and energy harvesting, the SINANO and NANOSIL networks, the STEEPER and E2SWITCH projects on energy efficient nanoelectronics. IUNET is also member of AENEAS and SINANO Institute.

The following third parties are linked to participant IUNET: University of Modena and Reggio Emilia and University of Udine. They will participate to IN-FET following a well established model already used in several EU projects of the H2020, 6th and 7th FP. The selected IUNET units will participate to IN-FET with clearly distinct roles associated to unique and required expertise. IUNET-Udine has long standing experience in semi-classical modelling of nanoelectronic devices and it will develop continuous models for nanowire sensors and iontronic devices. IUNET-Unimore will focus on ionic transport using a kinetic Monte-Carlo (k-MC) approach and will also collaborate with IUNET-Udine and other partners for selected characterizations of materials and design of optimized devices.

Description the partner’s main task in IN-FET

IUNET’s main role in IN-FET is in the modeling, simulation and electrical characterization of the sensor and ion actuation devices for the proposed platform aimed at supporting device design and interpretation of the experimental results. Two partners of IUNET will participate to the project: University of Modena and Reggio Emilia (IUNET-UniMORE) and University of Udine (IUNET-UniUD), each with a clear and distinct role. IUNET will contribute with its expertise in modeling and simulation of electron devices based on electronic and ionic transport and its ability to derive from physics-based models new circuit level representations that enable simulations at a higher level of abstraction. It will develop and use advanced multiscale / multiphysics modeling and simulation tools based on continuum (mainly Univ. of Udine) and compact/discrete models (mainly Univ. of Modena and Reggio Emilia) for physical systems and electronic circuits. The models will enable extensive simulations of device variants. Furthermore, IUNET will carry out selected electrical characterizations for model calibration and verifications.

Description and CV of the personnel carrying out the project

Luca Selmi (male) received the PhD in Electronic Engineering from University of Bologna in 1992. Since 2000 he has been Professor of Electronics (University of Udine, Italy); in 2017 he moved to University of Modena and Reggio Emilia, Italy. His research interests are in the field of electron device and sensor modelling and characterization, with emphasis on nanoscale CMOS devices, Nonvolatile memories, ISFETs and impedance sensing devices. He held technical and coordination responsibility in more than 10 EC projects and several national projects. He has been coordinator of the FP7 project III-V-MOS. He is TPC member of VLSI Tech. Symp. and has been general chair of INFOS and IEEE ICMTS. He co-authored about 300 refereed papers, (more than 40 at IEDM), and received about 4900 cites. He is Editor of IEEE-EDL. In 2015 he has been elevated to the IEEE Fellow grade. He is currently director of the IUNET consortium.

Pierpaolo Palestri (male) received the Laurea Degree in Electronic Engineering from the University of Bologna, Italy, in 1998, and the Ph.D. in Electronic Engineering from the University of Udine, Italy, in 2003. From July 2000 to September 2001 he held a post-doctoral position at Bell Laboratories, Lucent Technologies (then Agere Systems), Murray Hill, NJ, where he worked on high-speed silicon-germanium bipolar technologies. In 2005 he became Associate Professor at the University of Udine. His research interests include the modeling of nanoscale devices, carrier transport, hot-carrier and tunneling phenomena and Non-Volatile-Memory cells, as well as the design of integrated circuits for high-frequency applications. Pierpaolo Palestri has coauthored about 250 paper in international journal and conferences with peer review (about 10 invited) and 8 book chapters. He held technical and coordination roles in several European and national projects and is currently coordinator of a MIUR PRIN project on avalanche photodetectors for medical and synchrotron physics applications.

Paolo Pavan (male) is Professor of Electronics at the University of Modena and Reggio Emilia. He is Senior Member of the IEEE. He is now Associate Editor for the IEEE Journal of Electron Device Society. His research interests are in the field of electrical characterization and modeling of solid-state devices. He cooperates with italian and foreign companies for the development and optimization of new semiconductor memories. Presently he is working on characterization and compact modeling of innovative nonvolatile semiconductor memories based on RRAM technology, that can be used as artificial synapses. The developed compact models allow users to design neuro-inspired architectures based on synapses realized with HfO2 RRAM.

Luca Larcher (male) received the Ph.D. degree in “Information Engineering” from the University of Modena and Reggio Emilia in 2002. He is currently Professor of Electronics. His research interests extend to the modeling and characterization of physical mechanisms governing the charge transport and degradation in dielectrics, with applications to CMOS technologies, compact modeling of electron deivces, charge trapping in memory devices based on innovative materials for nanoeletronics, and the design of CMOS integrated circuits for More than Moore applications. He has joined and lead research projects in collaboration with international research centres (CEA-LETI, IMEC, TYNDALL, SEMATECH, POSTECH) and companies (RCF, FBT, ASK, STM, MDLab, COBO, DIECI) supported by regional, national and European programs (ENIAC Mirandela, END and LAB2MEMS-II, NoE Nanofuction, IP GOSSAMER). In 2013 he co-founded MDLab, developing and marketing simulation software for electron devices based on electronic and ionic transport. He authored and co-authored a book and more than 200 technical papers published on international journals and proceedings of international conferences and receiving more than 4500 citations and H-factor is 37. He has been technical and executive committee member of the IEEE-IEDM (twice), IEEE-IRPS (twice). He is currently Technical Program Chair of IIRW.

List of previous projects/activities relevant for IN-FET

  • CONVERGENCE, Flag-ERA (2017-2020); “Frictionless Energy Efficient Convergent Wearables For Healthcare And Lifestyle Applications”, partner, WP and task leader.
  • NANOFUNCTION, CSA, FP7; (2013-2016); “Beyond CMOS Nanodevices for Adding Functionalities to CMOS”, partner – modeling and simulation of sensor devices
  • III-V-MOS, STREP, FP7, (2013-2016); “Technology CAD for III-V Semiconductor-based MOSFETs”, coordinator, WP leader – modeling and simulation of III-V MOS transistor down to nanoscale dimensions
  • NEREID, CSA, H2020 (2015-2018); “Nanoelectronics Roadmap for Europe: Identification and Dissemination”, partner, WP leader, scientific expert
  • STEEPER, STREP, FP7 (2012-2016); “Steep subthreshold slope switches for energy efficient electronics”, partner, WP leader – semiclassical and quantum modeling of steep slope devices.
  • E2SWITCH, STREP, FP7 (2013-2017); “Energy Efficient Tunnel FET Switches and Circuits”, partner –modeling of tunnel-FETs devices and circuits.

Description of infrastructures relevant for IN-FET

IUNET leverages excellent laboratory and computational facilities of the partner Universities. The IUNET units participating to the project have adequate computer hardware, software licenses (SDevice TCAD platform, MATLAB, etc.) and in-house developed simulators based on semi-classical continuum and discrete models for electron devices and electrolyte interfaces with electronic and ionic transport. The units’ electron device characterization laboratories are equipped with state-of-the-art instrumentation for on-wafer electrical measures in dc, ac, transient and rf regimes, especially those down to extremely low current values. An advanced nanoelectrode-array impedance spectroscopy sensor platform is also available for selected characterizations in liquid environment.

List of selected relevant publications

  • C. Laborde et al., “Real-time imaging of microparticles and living cells with CMOS nanocapacitor arrays”, Nature Nanotech., 2015, DOI: 10.1038/NNANO.2015.163.
  • A. Bandiziol, et al., “A TCAD-Based Methodology to Model the Site-Binding Charge at ISFET/Electrolyte Interfaces”, IEEE T-ED, 2015, doi: 10.1109/TED.2015.2464251.
  • P. Scarbolo et al., “Characterization and modelling of differential sensitivity of nanoribbon-based pH-sensors”, Proc. 2015 Transducers, pp. 2188-2191.
  • P. Palestri, et al., Sensitivity of Silicon Nanowire Biochemical Sensors, in Beyond-CMOS Nanodevices, Wiley, pag. 43-63, 2014, ISBN 978-1-848216549.
  • E.Accastelli, et al., “Multi-Wire Tri-Gate Silicon Nanowires Reaching Milli-pH Unit Resolution in One Micron Square Footprint”, Biosensors 2016, 6(1), 9; doi:10.3390/bios6010009.
  • A.Cossettini et al., “On the Response of Nanoelectrode Impedance Spectroscopy Measures to Plant, Animal, and Human Viruses”, accepted for publication, IEEE Trans. on NanoBioScience, 2018, doi: 10.1109/TNB.2018.2826919.
  • F. M. Puglisi et al., “Energy-Efficient Logic-in-Memory 1-bit Full Adder Enabled by a Physics-Based RRAM Compact Model”, accepted for publication, Proc. ESSDERC 2018.
  • J. Woo et al., “Linking Conductive Filament Properties and Evolution to Synaptic Behavior of RRAM Devices for Neuromorphic Applications,” IEEE EDL, pp. 1220, 2017, doi: 10.1109/LED.2017.2731859.
  • L. Larcher et al., “Multiscale modeling of neuromorphic computing: From materials to device operations,” Proc. IEEE IEDM 2017, doi: 10.1109/IEDM.2017.8268374.

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